This invention relates to field emission cathode techniques, and more particularly to a field emission cathode known to be a cold cathode in the art and a method for manufacturing the same.
When an electric field set to be about 10.sup.9 (V/m) is applied to a surface of a metal material or that of a semiconductor material, a tunnel effect occurs to permit electrons to pass through a barrier, resulting in the electrons being discharged to a vacuum even at a normal temperature. Such a phenomenon is referred to as "field emission" in the art and a cathode constructed so as to emit electrons based on such a principle is referred to as a "field emission cathode" or "field emission element" in the art.
Recently, development of semiconductor fine-processing techniques permits a field emission cathode (hereinafter also referred to as "FEC") of the surface emission type to be constructed of field emission cathode elements having a size as small as microns. Arrangement of the thus-constructed field emission cathodes in large numbers on a substrate is expected to permit the field emission cathodes to act as an electron source for a display device of the flat type or various electronic devices.
Such a conventional field emission cathode is typically represented by an field emission cathode (FEC) of the Spindt type by way of example, which is generally constructed in such a manner as shown in FIG. 4.
More particularly, the FEC includes a substrate 100 on which a cathode electrode layer 101 is formed. Then, the cathode electrode layer 101 is depositedly formed thereon with a resitive layer 102, an insulating layer 103 and a gate electrode 104 in a film-like manner in order. The insulating layer 103 is formed with holes, in each of which an emitter 115 of a conical shape is arranged in a manner to be exposed at a tip end thereof through each of apertures of the gate electrode layer 104 formed so as to respectively communicate with the holes of the insulating layer 103.
Use of fine processing tehcniques for manufacturing of such an FEC permits a distance between the conical emitters 115 and the gate electrode layer 104 to be reduced to a level lower than a micron, so that application of a voltage as low as tens of volts between the conical emitters 115 and the gate electrode layer 104 permits the conical emitters 115 to discharge electrons.
Thus, when voltages VGE and VA are applied to a display device wherein an anode substrate 116 having a phosphor material deposited thereon is arranged above the substrate 100 on which a number of FECs are arranged in an array as shown in FIG. 4, electrons emitted from the FECs are permited to impinge on the phosphor material, resulting in the phosphor material emitting light.
Now, reasons for which the resistive layer 102 is arranged between the conical emitters 115 and the cathode electrode layer 101 will be described hereinafter.
A distance between the conical emitters 115 and gate electrodes is highly decreased, to thereby often cause short-circuiting therebetween due to dust or the like entering a gap therebetween during manufactuing of the display device. When such short-circuiting occurs even in one place, application of a voltage between the gate electrode and the conical emitters is failed, leading to a failure in operation of the display device.
Also, the FEC locally produces gas during initial operation thereof, which gas often causes discharge to occur between the conical emitters and the gate electrodes or anode electrodes, resulting in a large amount of current flowing through the cathode electrodes, leading to breakage of the cathode electrodes.
Further, of a number of conical emitters, conical emitters apt to easily emit electrons concentratedly carries out emission of electrons, so that a current is caused to focus on the conical emitters. This results in excessively bright spots often occurring on an image plane.
The resistive layer 102 arranged between the conical emitters 115 and the cathode electrode layer 101 as described above, when certain conical emitters 115 excessively emit electrons, permits a voltage drop to occur in a direction of restraining excessive emission of electrons from the conical emitters 115 depending on an increase in current flowing to the conical emitters 115, resulting in excessive emittion of electrons from the emitters being substantially prevented. Thus, arrangement of the resistive layer 102 contributes to an increase in yields of the FECs manufactured and stable operation of the display device.
Now, manufacturing of the FEC of the spindt type constructed as described above will be described hereinafter with reference to FIGS. 5(a) to 5(e) by way of example.
First, as shown in FIG. 5(a), the substrate 100 made of glass or the like is formed thereon with a film of niobium (Nb), resulting in the conductive layer 101 in the form of a thin film being provided thereon. Thereafter, .alpha.-Si (amorphous silicon) doped with an impurity is deposited in the form of a film on the thin film conductive layer 101 by chemical vapor deposition (CVD), to thereby provide the resistive layer 102 and then SiO.sub.2 (silicon dioxide) is deposited in the form of a film on the resistive layer 102, to thereby provide the insulating layer 103. Subsequently, Nb is deposited in the form of a film on the insulating layer 103 by sputtering, to thereby provide the gate electrode layer 104, resulting in a laminate being provided.
Then, a photoresist layer 111 is applied onto the gate electrode layer 104 which is a frontmost or uppermost layer of the laminate and then a mask 112 is arranged on the photoresist layer 111, followed by patterning of the photoresist layer 111 by photolithography, resulting in an aperture pattern being formed on the photoresist layer 111.
Subsequently, the laminate is subject to anisotropic etching by means of any suitable gas such as SF.sub.6 or the like on a side thereof on which the photoresist layer 111 is deposited. For this purpose, reactive ion etching (RIE) is employed. This results in the gate electrode layer 104 being formed with apertures 113 of the same pattern as the aperture pattern of the photoresist layer 111, as shown in FIG. 5(b).
Thereafter, the lamitate is subject to dry etching, leading to anisotropic etching of the insulating layer 103. This results in the insulating layer 103 being formed with holes 114 as shown in FIG. 5(c). Then, the laminate is subject to oblique deposition of aluminum (Al) by vapor deposition while being rotated in the same plane. This results in Al being selectively applied onto only a surface of the gate electrode layer 104 as shown in FIG. 5(c) while being kept from being deposited in the holes 114, resulting in a peel layer 105 being formed.
Then, the laminate is depositedly formed on a side thereof on which the holes 114 are provided with molybdenum (Mo) for emitters. This results in Mo for the emitters being not only formed in the holes 114 while being deposited on the resistive layer 102, but deposited on the peel layer 105 as shown in FIG. 5(d). Mo deposited on the peel layer 105 is designated at reference numeral 106, so that the emitter material or Mo 106 deposited on the peel layer 105 closes the apertures and the emitter material or Mo deposited on the resistive layer 102 forms the conical emitters 115.
Then, the laminate is immersed in a phosphoric acid solution for dissolving the peel layer 105, so that the peel layer 105 and emitter material 106 on the gate electrode layer 104 may be removed, resulting in an FEC which has such a configuration as shown in FIG. 5(e) being provided.
When the conical emitters 115 are formed on the resistive layer 102 as shown in FIG. 4, a resistance between each of cathode wirings for the cathode electrode layer 101 and each of the conical emitters 115 is often veried depending on a distance between the cathode wiring and the conical emitter. More particularly, a resistance between each of the cathode wirings and each of the conical emitters 115 arranged in proximity to the cathode wirings is reduced, whereas that between each of the cathode wirings and each of the conical emitters 115 positioned in the middle of the conical emitter group, to thereby be apart from the cathode wirings is increased. This causes emission of electrons from the conical emitters arranged in proximity to the cathode wirings to be increased and that from the conical emitters away from the cathode wirings to be decreased, so that electron emission of the conical emitters is rendered non-uniform.
In order to eliminate such a disadvantage, the assignee proposed an FEC in which cathode electrodes are arranged in an island-like manner, as disclosed in Japanese Patent Application No. 20923/1993. The FEC proposed is constructed in such a manner as shown in FIG. 6. More particularly, a substrate 100 includes a cathode wiring region on which cathode wirings 121 are arranged. The region is formed with scooped-out portions, in which island-like cathode electrodes 122 are arranged while being separated from the cathode wirings 121. Then, a plurlaity of conical emitters 126 for each emitter group are arranged above each of the island-like cathode electrodes 122 in a manner to positionally correspond thereto. Such construction permits a resistance between each of the cathode wirings and each of the conical emitters 126 for each emitter group to be uniform, so that electron emission of the conical emitters may be rendered uniform.
The FEC constructed as shown in FIG. 4 causes the resistive layer 102 made of .alpha.-Si to be reduced in resistance, resulting in an emission current discharged from the conical emitters 115 being increased with an increase in enveronmetal temperature. Such characteristics of the FEC causes various disadvantages to be exhibited when a display device including such FECs is arranged on a vehicle mounted equipment, because the equipment is substantially increased in temperature variation.
Also, when formation of the holes 114 in the insulating layer 102 in manufacturing of the FEC is carried out by dry etching as shown in FIG. 5(c), the resistive layer 102 made of .alpha.-Si is caused to be partially etched. This causes a surface of the resistive layer 102 made of .alpha.-Si to be deteriorated, resulting in a failure in satisfactory adhesion between the resistive layer 102 and the conical emitters 115 formed on the resistive layer 102, leading to a problem of causing the conical emitters 115 to be easily peeled from the resitive layer 102.
Further, the FEC having the cathode electrodes arranged in an island-like manner as shown in FIG. 6 is varied in field emission characteristics depending on a resistance between the conical emitters 125 and the island-like cathode electrodes 122 and that between the island-like cathode electrodes 122 and the cathode wirings 121. More particularly, a decrease in resistance between the conical emitters 126 and the island-like cathode electrodes 122 causes uniformity of an emission current discharged from the conical emitters to be deteriorated, whereas an increase in resistance therebetween causes a voltage across a gate electrode 125 acting as a lead-out electrode to be increased.
An approach to the problem is proposed which is constructed in such a manner that a resistive layer 123 is made of a material increased in resistivity to increase a resistance between the conical emitters 126 and the island-like cathode electrodes 122 and a gap between the cathode wirings 121 and the island cathode electrodes 122 is reduced to decrease a resistance between the cathode wirings 121 and the island cathode electrodes 122. Unfortunately, the approach requires fine processing, to thereby render a manufacturing process of the FEC highly complicated.
Also, another approach is proposed which is adapted to increase a thickness of the resistive layer 123. The approach provides substantially the same advantage as in an increase in resistivity of the resistive layer 123. However, step coverage characteristics of an insulating layer 124, the gate electrode layer 125 and the like render practicing of the approach substantially impossible.